Today sureCore Ltd announced that it has secured a Technology Strategy Board SMART award of £250K to help realise the company’s low power SRAM technology in a leading edge next generation silicon process node. Working with the major foundries developing FDSOI and FinFET technologies the grant will be used to contribute to the development of a demonstrator chip which will be used to showcase sureCore’s patented array control and sensing scheme which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models sureCore has designed an SRAM memory consuming less than half the power of existing solutions.

Paul Wells, CEO of sureCore, commented “We are pleased that the TSB has recognised the potential of our technology by awarding this grant. We have proven the technology in simulation but to fully characterise and demonstrate its benefits implementation in silicon is a must. This is a critical next step in demonstrating the value of our IP to our customers.