Following the recent launch of a range of cryogenic IP after the successful evaluation of test chips in both 180 nm and 22nm process nodes, sureCore has teamed with packaging experts, Sarcina, who designed a custom package specifically for use at cryogenic temperatures.

Paul Wells, sureCore’s CEO, explained, “This represents another critical step in our programme to make Cryo-CMOS available for the quantum computing ecosystem. Our CryoMem™ range of memory IP is silicon proven in addition to validating our library recharacterization service. We are also offering a range of cryogenic design capabilities to help quantum computing companies design the control/interface chips which need to be migrated into the cryostat alongside the qubits. Reliable, robust, cryo-ready chip packaging is a necessity in these harsh, low temperature environments and to ensure this we partnered with Sarcina whose specialist package design expertise is second to none.”

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