KU Leuven in Belgium is using IP from SureCore to reduce dynamic power in an AI chip by 40%.

The PowerMiser IP was used in a 16nm FinFET process and can reduce dynamic power by up to 50% and static/leakage power by up to 20% compared to foundry and other SRAM solutions, with savings across the full process, voltage and temperature range. SureCore in Sheffield, UK, is planning a 7nm variant of the technology.

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