Sheffield, England, March 2014 – sureCore Ltd has today announced that early testing of its innovative low power SRAM design confirms its simulations that deliver in excess of 50% power savings over other SRAM technologies.

The tests prove that the patented circuit architecture developed by sureCore delivers greater than 50% power savings versus industry standard SRAMs. sureCore’s energy-efficient memory was designed through a unique combination of detailed circuit analysis, architectural improvements, and the use of advanced statistical models.

sureCore’s solution is technology independent and is applicable to Bulk CMOS, FinFET and FD-SOI technologies.

Paul Wells, sureCore CEO, said: “This is a tremendous achievement by our engineering team; right first time silicon at 28nm and performance measurements correlating exceptionally well with simulation. This demonstrates the immense capability of our technology and the expertise of our engineers to deliver next generation SRAM. Silicon verification of our design defines a major milestone in our relationships with partners and customers.”

sureCore’s Chairman and industry veteran, Guillaume d’Eyssautier commented: “These early evaluation results are excellent and show that this approach delivers game-changing power performance for emerging low power applications such as the Internet-of-Things. This performance could double battery life in power critical applications and brings the ‘fit-and-forget’ approach to distributed sensor networks a crucial step closer.”

sureCore will target this technology, and its significant efficiency advantages, at the mobile, networking and wearable technology markets, where power is critical.